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RISC-V hardware modification for M-sequences generationA hardware modification of the soft processor core of the open RISC-V architecture to accelerate
CORDIC-lifting factorization of paraunitary filter banks based on the quaternionic multipliers for lossless image coding. Lifting allows for making multiplications invertible. The 2D CORDIC engine using sparse iterations
Thresholding Neural Network Image Enhancement Based on 2-D Non-separable Quaternionic Filter BankThe thresholding neural network with a 2-D non-separable paraunitary filter bank based
Image enhancement by 2D non-separable quaternionic filter bank-based thresholding neural networkThe thresholding neural network with a 2-D non-separable paraunitary filter bank based
2-D non-separable integer implementation of paraunitary filter bank based on the quaternionic multiplier block-lifting structureThis paper presents a novel technique of factorization for 2-D non-separable quaternionic
High performance multiplier-less pipelined FPGA architecture for 2-D non-separable quaternionic filter banksThis paper presents a systematic design of the 2-D non-separable quaternionic paraunitary filter
Rate-distortion estimation of 2-D non-separable filter banks based on quaternionic filter banks with JPEG2000 discrete wavelet transformsRate-distortion estimation of 2-D non-separable filter banks based on quaternionic filter banks
Multiplierless structurally orthogonal block-lifting-based quaternionic paraunitary filter banks with sum of-powers-of-two coefficients
Design and implementation of reversible integer quaternionic paraunitary filter banks on adder-based distributed arithmetic
Embedded distributed arithmetic based quaternions multiplier of paraunitary filter bank for lossless-to-lossy image coding
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