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A fault-tolerant combinational circuit design
Ostanin, S. A., Kirienko, I. E., Lavrov, V. A.
A fault-tolerant combinational circuit design
A fault-tolerant sequential circuit design for soft errors based on fault-secure circuit
Ostanin, S. A., Butorina, Natalia Borisovna, Lavrov, V. A., Matrosova, Anjela Yu.
A fault-tolerant sequential circuit design for soft errors based on fault-secure circuit
A fault-tolerant sequential circuit design for SAFs and PDFs soft errors
Matrosova, Anjela Yu., Kirienko, I. E., Nikolaeva, E. A., Ostanin, S. A.
A fault-tolerant sequential circuit design for SAFs and PDFs soft errors
Patching circuit design based on reserved CLBs
Matrosova, Anjela Yu., Ostanin, S. A., Andreeva, V.
Detection and masking of Trojan Circuits in sequential logic
Mitrofanov, Evgenii V., Ostanin, Sergey A., Nikolaeva, Ekaterina A., Matrosova, Anjela Yu.
A technique of finding a set of sequential circuit
Preventing and masking Trojan Circuits triggering out of working area
Mitrofanov, Evgenii V., Ostanin, Sergey A., Kirienko, Irina E., Matrosova, Anjela Yu.
Inserting malicious sub-circuits that may cause a
Fault-tolerant synchronous FSM network design for path delay faults
Andreeva, V. V., Butorina, Natalia B., Tretyakov, D., Ostanin, Sergey A.
Finding false paths for sequential circuits using operations on ROBDDs
Matrosova, Anjela Yu., Ostanin, Sergey A., Chernyshov, Semen V.
Квалификация, верификация и валидация
Агафонов, С. А., Кузнецов, А. Н., Останин, С. М., Agafonov, S. A., Kuznetsov, A. N., Ostanin, S. M.
Fully delay and multiple stuck-at fault testable sequential circuit design
Matrosova, A. Yu., Nikolaeva, E. A., Kirienko, I. E., Ostanin, S. A.

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